1. Field of the Invention
The present invention relates generally to the chemical mechanical planarization (CMP) of substrates, and more particularly, to techniques for end-point detection in CMP.
2. Description of the Related Art
In the fabrication of semiconductor devices, there is a need to perform CMP operations, including planarization, buffing and substrate cleaning. Typically, integrated circuit devices are in the form of multi-level structures. At the substrate level, transistor devices having diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define the desired functional device. As is well known, patterned conductive layers are insulated from other conductive layers by dielectric materials, such as silicon dioxide. At each metallization level there is a need to planarize metal or associated dielectric material. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other applications, metallization line patterns are formed in the dielectric material, and then metal CMP operations are performed to remove excess metallization, e.g., such as copper.
In the prior art, CMP systems typically implement belt, orbital, or brush stations in which belts, pads, or brushes are used to scrub, buff, polish and otherwise prepare a substrate. In some applications, an abrasive substance in suspension, known as slurry, is used to facilitate and enhance the CMP operation. Slurry is most usually introduced onto a moving preparation surface, e.g., belt, pad, brush, and the like, and distributed over the preparation surface as well as the surface of the substrate being buffed, polished, or otherwise prepared by the CMP process. The distribution is generally accomplished by a combination of the movement of the preparation surface, the movement of the semiconductor wafer and the friction created between the semiconductor wafer and the preparation surface.
FIG. 1A shows a cross sectional view of a dielectric layer 102 undergoing a fabrication process that is common in constructing damascene and dual damascene interconnect metallization lines. The dielectric layer 102 has a diffusion barrier layer 104 deposited over the etch-patterned surface of the dielectric layer 102. The diffusion barrier layer 104, as is well known, is typically titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination of tantalum nitride (TaN) and tantalum (Ta). Once the diffusion barrier layer 104 has been deposited to the desired thickness, a metal layer, e.g., copper, 104 is formed over the diffusion barrier layer in a way that fills the etched features in the dielectric layer 102. Some excessive diffusion barrier and metallization material is also inevitably deposited over the field areas. In order to remove these overburden materials and to define the desired interconnect metallization lines and associated vias (not shown), a metal chemical mechanical planarization (CMP) operation is performed.
As mentioned above, the metal CMP operation is designed to remove the top metallization material from over the dielectric layer 102. For instance, as shown in FIG. 1B, the overburden portion of the copper layer 106 and the diffusion barrier layer 104 have been removed. As is common in CMP operations, the CMP operation must continue until all of the overburden metallization and diffusion barrier material 104 is removed from over the dielectric layer 102. However, in order to ensure that all the diffusion barrier layer 104 is removed from over the dielectric layer 102, there needs to be a way of monitoring the process state and the state of the wafer surface during the CMP processing. This is commonly referred to as end-point detection. In multi-step CMP operations there is a need to ascertain multiple end-points (e.g., such as to ensure that the copper (Cu) is removed from over the diffusion barrier layer; and to ensure that the diffusion barrier layer is removed from over the dielectric layer). Thus, end-point detection techniques are used to ensure that all of the desired overburden material is removed. A common problem with current end-point detection techniques is that some degree of over-processing, also known as over-polishing, is required to ensure that all of the conductive material (e.g., metallization material or diffusion barrier layer 104) is removed from over the dielectric layer 102 to prevent inadvertent electrical interconnection between metallization lines.
One side effect of improper end-point detection or over-polishing is that dishing 108 occurs over the metal features that remain within the dielectric layer 102. The dishing effect essentially removes more metallization material than desired and leaves a dish-like top surface over the metallization lines. Dishing is known to impact the performance of the interconnect metallization lines in a negative way, and too much dishing can cause a desired integrated circuit to fail for its intended purpose.
Dishing further contributes to a non-uniform thickness of layers in a semiconductor wafer. As is known, some circuit fabrication applications require that a specific thickness of material be maintained in order to craft a working device. By way of example, the dielectric layer 102 needs to be maintained at a specific thickness to accommodate the metallization lines and associated conductive vias defined therein.
One way of performing end-point detection is to use an optical detector. Using optical detection techniques, it is possible to ascertain a level of removal of certain films from the wafer surface. This optical detection technique is designed to detect changes in the wafer surface composition by inspecting the interference patterns received by the optical detector. Although optical end-point detection is suitable for some applications, optical end-point detection may not be adequate in cases where end-point detection is desired for different regions or zones of the semiconductor wafer.
FIG. 2A shows a partial cross-sectional view of an exemplary semiconductor chip 201 after the top copper layer has undergone a CMP process. Using standard impurity implantation, photolithography, and etching techniques, P-type transistors and N-type transistors are fabricated into the P-type silicon substrate 200. As shown, each transistor has a gate, source, and drain, which are fabricated into appropriate wells. The pattern of alternating P-type transistors and N-type transistors creates a complementary metal dielectric semiconductor (CMOS) device.
A first dielectric layer 202 is fabricated over the transistors and substrate 200. Conventional photolithography, etching, and deposition techniques are used to create tungsten plugs 210 and copper lines 212. The tungsten plugs 210 provide electrical connections between the copper lines 212 and the active features on the transistors. A second dielectric layer 204 may be fabricated over the first dielectric layer 202 and copper lines 212. Conventional photolithography, etching, and deposition techniques are used to create copper vias 220 and copper lines 214 in the second dielectric layer 204. The copper vias 220 provide electrical connections between the copper lines 214 in the second layer and the copper lines 212 or the tungsten plugs 210 in the first layer.
The wafer then typically undergoes a copper CMP process to remove the overburden metallization material leaving metal only in the trenches, and the entire wafer surface as flat as possible as described with reference to FIGS. 1A-1B. After the copper CMP process, the wafer is cleaned in a wafer cleaning system.
FIG. 2B shows the partial cross-sectional view after the wafer has undergone optical end-point detection. As shown, the copper lines 214 on the top layer have been subjected to photo-corrosion during the detection process. The photo-corrosion is believed to be partially caused by light photons emitted by the optical detector and reach the P/N junctions, which can act as solar cells. Unfortunately, this amount of light, which is generally normal for optical detection, can cause a catastrophic corrosion effect.
In this cross-sectional example, the copper lines, copper vias, or tungsten plugs are electrically connected to different parts of the P/N junction. The slurry chemicals and/or chemical solutions applied to the wafer surface, can include electrolytes, which have the effect of closing an electrical circuit as electrons exe2x88x92 and holes h+ are transferred across the P/N junctions. The electron/hole pairs photo-generated in the junction are separated by the electrical field. The introduced carriers induce a potential difference between the two sides of the junction. This potential difference increases with light intensity. Accordingly, at the electrode connected to the P-side of the junction, the copper is corroded: Cuxe2x86x92Cu2++2exe2x88x92. The produced soluble ionic species can diffuse to the other electrode, where the reduction can occur: Cu2++2exe2x88x92xe2x86x92Cu. Note that the general corrosion formula for any metal is Mxe2x86x92Mn++nexe2x88x92, and the general reduction formula for any metal is Mn++nexe2x88x92xe2x86x92M. For more information on photo-corrosion effects, reference can be made to an article by A. Beverina et al., xe2x80x9cPhoto-Corrosion Effects During Cu Interconnection Cleanings,xe2x80x9d to be published in the 196th ECS Meeting, Honolulu, Hi. (October 1999). This article is hereby incorporated by reference.
Photo-corrosion displaces the copper lines and destroys the intended physical topography of the copper features, as shown in FIG. 2B. At some locations on the wafer surface over the P-type transistors, the photo-corrosion effect may cause corroded copper lines 224 or completely dissolved copper lines 226. In other words, the photo-corrosion may completely corrode the copper line such that the line no longer exists. On the other hand, over the N-type transistors, the photo-corrosion effect may cause copper deposit 222 to be formed. This distorted topography, including the corrosion of the copper lines, may cause device defects that render the entire chip inoperable. One defective device means the entire chip must be discarded, thus, decreasing yield and drastically increasing the cost of the fabrication process. This effect, however, will generally occur over the entire wafer, thus destroying many of the chips on the wafer. This, of course, increases the cost of fabrication.
In view of the foregoing, there is a need for CMP end-point detection systems that do not implement optical detectors and enable precision end-point detection to prevent dishing and avoid the need to perform excessive over-polishing.
Broadly speaking, the present invention fills these needs by providing a system and method for using infrared emissions to determine process state, and to produce an infrared surface map of a substrate during CMP processing of substrates. The present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a method, or a computer readable media. Several embodiments of the present invention are described below.
In one embodiment, a chemical mechanical planarization system is disclosed. The system includes a substrate chuck that holds and rotates a substrate with at least one fabricated layer to be CMP processed. The system further includes a preparation carrier with a preparation head that is applied to a preparation surface of the substrate, such that the preparation head overlaps at least a portion of the preparation surface of the substrate that is less than an entire portion of the preparation surface of the substrate. Finally, the system includes an infrared sensor that senses infrared emission from the preparation surface of the substrate.
In another embodiment, a method for monitoring the process state of a wafer surface during chemical mechanical planarization is disclosed. The method includes joining the preparation surface and the wafer surface to remove a first layer of material from the wafer surface. The method further provides for the sensing of infrared emissions from the wafer surface during the removal of the first layer of material to determine and monitor the process state of the wafer.
In still a further embodiment, a method of end point detection is disclosed. The method includes providing a wafer that has a first layer of material to be removed from the preparation surface of the wafer, and providing a polishing pad. The method next creates frictional contact between the preparation surface of the wafer and the polishing pad to remove the first layer of material. Finally, the method provides for the sensing of infrared emissions from the preparation surface of the wafer during the removing of the first layer of material; and evaluating the infrared emissions to determine an end point of processing.
The advantages of the present invention are numerous. One notable benefit and advantage of the invention is the exploitation of infrared emissions provides an accurate determination of process end point, and avoids the prior art problems of photo-corrosion. Another benefit is the combination of infrared clearance detection with Variable Partial pad-wafer Overlap CMP processing which yields a precise and controllable CMP process. An additional benefit is the ability to utilize infrared sensing to generate infrared mapping of the entire surface of the substrate during CMP processing. In addition to process state, the infrared mapping reveals surface topography and composition, resulting in more precise semiconductor fabrication.